Field
Embodiments described herein relate to semiconductor packaging. More particularly, embodiments relate to system in package (SiP) structures and methods of fabrication.
Background Information
The current market demand for portable and mobile electronic devices such as mobile phones, personal digital assistants (PDAs), digital cameras, portable players, gaming, and other mobile devices requires the integration of more performance and features into increasingly smaller spaces. As a result, various multiple-die or component packaging solutions such as system in package (SiP) have become more popular to meet the demand for higher die/component density devices. There are many different possibilities for arranging multiple die in an SiP. For example, vertical integration of die in SiP structures has evolved into 2.5D solutions and 3D solutions. In 2.5D solutions the multiple die may be flip chip bonded on an interposer that includes through vias as well as fan out wiring. In 3D solutions multiple die may be stacked on top of one another on an SiP substrate, and connected with off-chip wire bonds or solder bumps.
There are additionally various degrees of SiP integration for an integrated product. In one implementation a number of small SiPs are mounted in a larger SiP, which is known as a package in package (PiP). In another implementation an SiP is mounted on top of another SiP, which is known as a package on package (PoP). SiP and PoP structures may be assembled on an interposer to fan out electrical terminals for an integrated product.